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mf424 - 21 technical manual s1d15000 series technical manual ieee1394 controller technical manual s1d15000 series epson electronic devices website electronic devices marketing division first issue december,1992 u printed may,2001 in japan h b 4.5mm this manual was made with recycle paper, and printed using soy-based inks. technical manual lcd driver with ram s1d15 3 00 series http://www.epson.co.jp/device/
in pursuit of ?aving?technology , epson electronic devices. our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers?dreams. epson is energy savings. 4.5mm notice no parts of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export licence from teh ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2001, all rights reserved. i8088 and i8086 are registered trademarks of intel corporation. z80 is registered trademark of zilog corporation. v20 and v30 are registered trademarks of nippon electric corporation.
the information of the product number change starting april 1, 2001 the product number will be changed as listed below. to order from april 1, 2001 please use the new product number. for further information, please contact epson sales representative. configuration of product number l devices (example : s1d15605d00b100) s1 d 15605 d 00b1 00 packing specification specifications shape (d:chip, t:tcp, f:qfp) model number model name (d:lcd driver) product classification (s1:semiconductors) comparison table between new and previous number previous number new number sed1510d 0c s1d15100d00c * sed1510f 0c s1d15100f00c * sed1520d aa s1d15200d10a * sed1520d ab s1d15200d10b * sed1520f 0a s1d15200f00a * sed1520f aa s1d15200f10a * sed1521f 0a s1d15201f00a * sed1521f aa s1d15201f10a * sed1522f 0a s1d15202f00a * sed1522f aa s1d15202f10a * sed1526f 0a s1d15206f00a * sed1526f aa s1d15206f10a * sed1526f ba s1d15206f11a * sed1526f ea s1d15206f14a * sed1526f ey s1d15206f14y * sed1526t 0a s1d15206t00a * sed1528d bb s1d15208d11b * sed1528f 0a s1d15208f00a * sed1530d 0a s1d15300d00a * sed1530d 0b s1d15300d00b * sed1540d 0a s1d15400d00a * sed1540d 0b s1d15400d00b * sed1540f 0a s1d15400f00a * sed1560d 0b s1d15600d00b * previous number new number sed1560d ab s1d15600d10b * sed1561d 0b S1D15601d00b * sed1561d ab S1D15601d10b * sed1562d 0b s1d15602d00b * sed1565d 0b s1d15605d00b * sed1565d 1b s1d15605d01b * sed1565d 2b s1d15605d02b * sed1565d bb s1d15605d11b * sed1565d be s1d15605d11e * sed1565t 0 * s1d15605t00 ** sed1565t 0b s1d15605t00b * sed1566d 0b s1d15606d00b * sed1566d 1b s1d15606d01b * sed1566d 2b s1d15606d02b * sed1566d bb s1d15606d11b * sed1566t 0 * s1d15606t00 ** sed1567d 0b s1d15607d00b * sed1567d 1b s1d15607d01b * sed1567d 2b s1d15607d02b * sed1567d bb s1d15607d11b * sed1567t 0 * s1d15607t00 ** sed1568d 0b s1d15608d00b * sed1568d bb s1d15608d11b * sed1569d 0b s1d15609d00b *
previous number new number sed1569d bb s1d15609d11b * sed1570d 0a s1d15700d00a * sed1570d 0b s1d15700d00b * sed1575d 0b s1d15705d00b * sed1575d 3b s1d15705d03b * sed1575d ab s1d15705d10b * sed1575t 0 * s1d15705t00 ** sed1575t 0a s1d15705t00a * sed1575t 3 * s1d15705t03 ** sed1577d 0b s1d15707d00b * sed1577d 3b s1d15707d03b * sed1577t 0 * s1d15707t00 ** sed1577t 3 * s1d15707t03 ** sed1578d 0b s1d15708d00b * sed157ad 0b s1d15710d00b * sed157ad ab s1d15710d10b * sed157ad bb s1d15710d11b * sed157at 0a s1d15710t00a * sed15a6d 0b s1d15a06d00b * sed15a6d 1b s1d15a06d01b * sed15a6d 2b s1d15a06d02b * sed15a6t 0 * s1d15a06t00 ** sed15b1d 0b s1d15b01d00b * sed15b1d 1b s1d15b01d01b * sed15b1d 2b s1d15b01d02b * sed15b1t 0 * s1d15b01t00 **
s1d15100 series s1d15200 series s1d15210 series s1d15206 series s1d15300 series s1d15400 series s1d15600/601/602 series s1d15605 series s1d15700 series s1d15705 series s1d15710 series s1d15a06 series s1d15b01 series
contents selection guide 1. s1d15100 series 2. s1d15200 series 3. s1d15210 series 4. s1d15206 series 5. s1d15300 series 6. s1d15400 series 7. s1d15600/601/602 series 8. s1d15605 series 9. s1d15700 series 10. s1d15705 series 11. s1d15710 series 12. s1d15a06 series 13. s1d15b01 series
s1d15000 series selection guide
s1d15100d00c * al pad chip (sed1510d 0c ) 0.9 to 6.0 1.8 to 6.0 1/4 32 4 128 bit serial 18(internal) s1d15100f00c * qfp12-48pin (sed1510f 0c ) s1d15200 ***** 18(internal, (sed1520 * ** ) 2.4 to 7.0 3.5 to 13 1/8 to 1/32 61 16 2,560 bit 8 bit external) or chip, tcp after service parts 2(external) s1d15201 ***** 18(internal, (sed1521 * ** ) 2.4 to 7.0 3.5 to 13 1/8 to 1/32 80 C 2,560 bit 8 bit external) or chip, tcp after service parts 2(external) s1d15202 ***** 18(internal, (sed1521 * ** ) 2.4 to 7.0 3.5 to 13 1/8 to 1/32 69 8 2,560 bit 8 bit external) or chip, tcp after service parts 2(external) s1d15206d ** a * al pad chip (sed1526d * a ) s1d15206d ** b * 3.5 to 8-bit au bump chip (sed1526d * b ) 2.4 to 6.0 supply 1/8,1/9, 80 17 80 33 bit parallel 20 s1d15206f ** a * voltage 1/16,1/17 or serial qfp5-128pin (sed1526f * a ) 3 s1d15206t ** a * tcp (sed1526t * a ) s1d15208d ** a * al pad chip (sed1528d * a ) s1d15208d ** b * 3.5 to 8-bit au bump chip (sed1528d * b ) 2.4 to 6.0 supply 1/32,1/33 64 33 80 33 bit parallel 20 s1d15208f ** a * voltage or serial qfp5-128pin (sed1528f * a ) 3 s1d15208t ** a * tcp (sed1528t * a ) s1d15300d00a * al pad chip (sed1530d 0a ) s1d15300d10a * al pad chip (sed1530d aa ) 8-bit s1d15300d00b * 2.4 to 6.0 4.5 to 16 1/32,1/33 100 33 132 65 bit parallel C au bump chip (sed1530d 0b ) or serial s1d15300d10b * au bump chip (sed1530d ab ) s1d15300t10a * tcp (sed1530t aa ) s1d15301d00a * al pad chip (sed1531d 0a ) 8-bit s1d15301d00b * 2.4 to 6.0 4.5 to 16 1/64,1/65 132 C 132 65 bit parallel C au bump chip (sed1531d 0b ) or serial s1d15301t00a * tcp (sed1531t 0a ) s1d15302d00a * al pad chip (sed1532d 0a ) s1d15302d11a * al pad chip (sed1532d ba ) s1d15302d00b * 8-bit au bump chip (sed1532d 0b ) 2.4 to 6.0 4.5 to 16 1/64,1/65 100 33 132 65 bit parallel C s1d15302d11b * or serial au bump chip (sed1532d bb ) s1d15302t00a * tcp (sed1532t 0a ) s1d15302t11a * tcp (sed1532t ba ) ultra-low power consumption and on-chip ram make this series ideal for compact lcd- based equipment. n lcd drivers with ram for small- and medium-sized displays s1d15000 (sed1500) series part number duty segment common display ram (bits) microprocessor interface frequency (khz) package application/additional features lcd voltage range (v) supply voltage range (v) tcp : tape carrier package small segment-type lcd display. common and data interface. dc/dc 3 (s1d15206 * 00 ** ?v reg ) (s1d15206 * 14 ** ?no v reg ) dc/dc 3 (s1d15208 * 00 ** ?v reg ) (s1d15208 * 14 ** ?no v reg ) built-in power circuit for lcd (dc/dc 4) s1d15300d00 ** (sed1530 * 0 * ) common : right side s1d15300 * 10 ** (sed1530 * a * ) common : both side built-in power circuit for lcd (dc/dc 4) s1d15301 * 00 ** (sed1531 * 0 * ) common : right side built-in power circuit for lcd (dc/dc 4) s1d15302 * 00 ** (sed1532 * 0 * ) common : right side s1d15302 * 11 ** (sed1532 * b * ) common : left side
part number duty display ram (bits) microprocessor interface frequency (khz) package application/additional features lcd voltage range (v) supply voltage range (v) segment common 8-bit s1d15303d15b * 2.4 to 6.0 4.5 to 16 1/17 116 17 132 65 bit parallel C au bump chip (sed1533d fb ) or serial s1d15400d00a * al pad chip (sed1540d 0a ) s1d15400d00b * 2.4 to 7.0 3.5 to 11 1/3, 1/4 73 3, 4 2,560 bit 8-bit 18(internal) , au bump chip (sed1540d 0b ) parallel 4(external) s1d15400f00a * qfp5-100pin (sed1540f 0a ) s1d15600d00a * al pad chip (sed1560d 0a ) s1d15600d10a * al pad chip (sed1560d aa ) s1d15600d00b * 8-bit au bump chip (sed1560d 0b ) 2.4 to 6.0 6.0 to 16 1/48,1/49, 102 65 166 65 bit parallel 18 s1d15600d10b * 1/64,1/65 or serial au bump chip (sed1560d ab ) s1d15600t00b * tcp (sed1560t 0b ) s1d15600t26a * qtcp (sed1560t qa ) S1D15601d00a * al pad chip (sed1561d 0a ) S1D15601d00b * au bump chip (sed1561d 0b ) S1D15601d10b * 8-bit au bump chip (sed1561d ab ) 2.4 to 6.0 6.0 to 16 1/24,1/25, 134 33 166 65 bit parallel 18 S1D15601t00b * 1/32,1/33 or serial tcp (sed1561t 0b ) S1D15601t10b * tcp (sed1561t ab ) S1D15601t26a * qtcp (sed1561t qa ) s1d15602d00a * al pad chip (sed1562d 0a ) s1d15602d00b * 8-bit au bump chip (sed1562d 0b ) 2.4 to 6.0 6.0 to 16 1/16,1/17 150 17 166 65 bit parallel 18 s1d15602t00b * (1/5 bias) or serial tcp (sed1562t 0b ) s1d15602t26a * qtcp (sed1562t qa ) s1d15605d11b * au bump chip (sed1565d bb ) s1d15605d00b * au bump chip (sed1565d 0b ) s1d15605d01b * au bump chip (sed1565d 1b ) 8-bit s1d15605d02b * 1.8 to 5.5 4.5 to 16 1/65 132 65 132 65 bit parallel 33 au bump chip built-in power circuit (sed1565d 2b ) (1/7,1/9 bias) or serial for lcd (dc/dc 4) s1d15605t00a * tcp (sed1565t 0a ) s1d15605t00b * tcp (sed1565t 0b ) s1d15605t00c * tcp (sed1565t 0c ) built-in power circuit for lcd (dc/dc 4) common : left side no v ref built-in power circuit for lcd (dc/dc 3) s1d15600 * 00b * (sed1560 * 0b ) : 1/9 bias s1d15600 * 10b * (sed1560 * ab ) : 1/7 bias built-in power circuit for lcd (dc/dc 3) S1D15601 * 00b * (sed1561 * 0b ) : 1/7 bias S1D15601 * 10b * (sed1561 * ab ) : 1/5 bias built-in power circuit for lcd (dc/dc 3)
part number duty display ram (bits) microprocessor interface frequency (khz) package application/additional features lcd voltage range (v) supply voltage range (v) segment common tcp : tape carrier package s1d15606d11b * au bump chip (sed1566d bb ) s1d15606d00b * au bump chip (sed1566d 0b ) 8-bit s1d15606d01b * 1.8 to 5.5 4.5 to 16 1/49 132 49 132 65 bit parallel 33 au bump chip built-in power circuit (sed1566d 1b ) (1/6,1/8 bias) or serial for lcd (dc/dc 4) s1d15606d02b * au bump chip (sed1566d 2b ) s1d15606t00a * tcp (sed1566t 0a ) s1d15607d11b * au bump chip (sed1567d bb ) s1d15607d00b * au bump chip (sed1567d 0b ) s1d15607d01b * 8-bit au bump chip (sed1567d 1b ) 1.8 to 5.5 4.5 to 16 1/33 132 33 132 65 bit parallel 33 built-in power circuit s1d15607d02b * (1/5,1/6 bias) or serial au bump chip for lcd (dc/dc 4) (sed1567d 2b ) s1d15607t00b * tcp (sed1567t 0b ) s1d15607t00c * tcp (sed1567t 0c ) s1d15608d11b * 8-bit au bump chip (sed1568d bb ) 1.8 to 5.5 4.5 to 16 1/55 132 55 132 65 bit parallel 33 built-in power circuit s1d15608d00b * (1/6,1/8 bias) or serial au bump chip for lcd (dc/dc 4) (sed1568d 0b ) s1d15609d11b * au bump chip (sed1569d bb ) 8-bit s1d15609d00b * 1.8 to 5.5 4.5 to 16 1/53 132 53 132 65 bit parallel 33 au bump chip built-in power circuit (sed1569d 0b ) (1/6,1/8 bias) or serial for lcd (dc/dc 4) s1d15609t **** tcp (sed1569t xx * ) s1d15a06d00b * 8-bit au bump chip (sed15a6d 0b ) 1.8 to 5.5 4.5 to 16 1/55 102 55 102 65 bit parallel 33 reduced ext. parts s1d15a06t00a * or serial tcp built-in power circuit. (sed15a6t 0a * ) s1d15b01d00b * 8-bit au bump chip (sed15b1d 0b ) 1.8 to 5.5 4.5 to 16 1/65 132 65 132 65 bit parallel 33 built-in self-refreshing s1d15b01t00a * or serial tcp function. (sed15b1t 0a ) s1d15e00d00b * au bump chip (sed15e0d 0b ) 1.8 to 3.6 3.2 to 10 1/100 132 100 132 100 bit serial can be select 4-line mls driving s1d15e00t00a * tcp (sed15e0t 0a ) s1d15705d00b * 3.6 to 5.5 8-bit (sed1575d 0b ) 4.5 to 16 1/65 168 65 200 65 bit parallel 22 au bump chip built-in power circuit s1d15705d03b * 2.4 to 3.6 or serial for lcd (dc/dc 4) (sed1575d 3b ) s1d15705t00a * 3.6 to 5.5 8-bit (sed1575t 0a ) 4.5 to 16 1/65 168 65 200 65 bit parallel 22 tcp built-in power circuit s1d15705t03a * 2.4 to 3.6 or serial for lcd (dc/dc 4) (sed1575t 3a ) s1d15707d00b * 3.6 to 5.5 8-bit (sed1577d 0b ) 4.5 to 16 1/33 200 33 200 65 bit parallel 22 au bump chip built-in power circuit s1d15707d03b * 2.4 to 3.6 or serial for lcd (dc/dc 4) (sed1577d 3b ) s1d15707t00a * 3.6 to 5.5 8-bit (sed1577t 0a ) 4.5 to 16 1/33 200 33 200 65 bit parallel 22 tcp built-in power circuit s1d15707t03a * 2.4 to 3.6 or serial for lcd (dc/dc 4) (sed1577t 3a ) s1d15710d00b * 8-bit au bump chip (sed157ad 0b ) 1.8 to 5.5 4.5 to 18 1/65 224 65 224 65 bit parallel 22 built-in power circuit s1d15710t00a * or serial tcp for lcd (sed157at 0a * )
5. s1d15300 series rev. 1.4
C i C rev. 1.4 contents 1. description .................................................................................................................. .............................. 5-1 2. features ..................................................................................................................... ................................. 5-1 3. block diagram (s1d15300d00b * ) ........................................................................................................... 5-2 4. pad layout ................................................................................................................... ............................... 5-3 5. pin description .............................................................................................................. ........................... 5-5 6. functional description ....................................................................................................... ................. 5-8 7. commands ..................................................................................................................... ............................5-19 8. command setting (for refrence) ............................................................................................... ............5-24 9. absolute maximum ratings ..................................................................................................... ........... 5-27 10. electrical characteristics .................................................................................................. ............5-28 11. mpu interface (for reference) ............................................................................................... ................ 5-36 12. connection between lcd drivers .............................................................................................. .....5-37
s1d15300 series rev.1.4 epson 5C1 name duty lcd bias segment driver com driver display area remarks s1d15300d 00 ]] 1/33 1/5, 1/6 100 33 33 100 com single-side layout s1d15300d 10 ]] 1/33 1/5, 1/6 100 33 33 100 com dual-side layout s1d15301d 00 ]] 1/65 1/6, 1/8 132 0 65 132 s1d16700 is used as the com. s1d15302d 00 ]] 1/65 1/6, 1/8 100 33 65 200 com single-side, right-hand layout s1d15302d 11 ]] 1/65 1/6, 1/8 100 33 65 200 com single-side, left-hand layout s1d15305d 10 ]] 1/35 1/5, 1/6 98 35 35 98 com both-side layout type 2 [v reg temperature gradient: 0.00% / c] note: the s1d15300 series has the following subcodes depending on their shapes. (the s1d15300 examples are given.) s1d15300t **** : tcp (the tcp subcode differs from the inherent chip subcode.) s1d15300d **** : bear chips s1d15300d ** a * : al-pad chip s1d15300d ** b * : au-bump chip 1. description the s1d15300 series is a single-chip lcd driver for dot-matrix liquid crystal displays (lcds) which is directly connectable to a microcomputer bus. it accepts 8-bit serial or parallel display data directly sent from a microcomputer and stores it in an on-chip display ram. it generates an lcd drive signal independent of microprocessor clock. the use of the on-chip display ram of 65 132 bits and a one-to- one correspondence between lcd panel pixel dots and on-chip ram bits permits implementation of displays with a high degree of freedom. as a total of 133 circuits of common and segment outputs are incorporated, a single chip of s1d15300 can make 33 100-dot (16 16-dot kanji font: 6 columns 2 lines) displays, and a single chip of s1d15301 can make 65 132-dot (kanji font: 8 columns x 4 lines) displays when the s1d15301 is combined with the common driver s1d16700. the s1d15302 can display the 65 200-dot (or 12-column by 4-line kanji font) area using two ics in master and slave modes. as an independent static indicator display is provided for time-division driving, the low-power display is realized during system standby and others. no external operation clock is required for ram read/write opera- tions. accordingly, this driver can be operated with a minimum current consumption and its on-board low-current-consumption liquid crystal power supply can implement a high-performance handy display system with a minimum current consumption and a smallest lsi configuration. two types of s1d15300 series are available: one in which common outputs are arranged on a single side and the other in which common outputs are arranged on both sides. 2. features ? direct ram data display using the display ram. when ram data bit is 0, it is not displayed. when ram data bit is 1, it is displayed. (at normal display) ? ram capacity: 65 132 = 8580 bits high-speed 8-bit microprocessor interface allowing direct connection to both the 8080 and 6800. serial interface many command functions: read/write display data, dis- play on/off, normal/reverse display, page address set, set display start line, set column address, read status, all display on/off, set lcd bias, electronic contrast controls, read modify write, select segment driver direc- tion, power save series specifications (in cases of chip shipments) type 1 [v reg (built-in power supply regulating voltage) temperature gradient: -0.2% / c] name duty lcd bias segment driver com driver display area remarks s1d15300d 15 ]] 1/33 1/5, 1/6 100 33 33 100 com both-side layout s1d15302d 14 ]] 1/65 1/6, 1/8 100 33 65 200 com single-side, right-hand layout s1d15303d 15 ]] 1/17 1/5 116 17 17 116 com both-side layout s1d15304d 14 ]] 1/9 1/5 124 9 9 124 com single-side layout ? on-chip lcd power circuit: voltage booster, voltage regulator, voltage follower 4. on-chip electronic contrast control functions ultra low power consumption power supply voltages: v dd - v ss -2.4 v to -6.0 v v dd - v5 -4.5 v to -16.0 v wide operating temperature range: ta = -40 to 85 c cmos process package: tcp and bare chip non-radiation-resistant design
s1d15300 series 5C2 epson rev.1.4 3. block diagram (s1d15300d00b * ) o0 o99 o100 o15 v 2 v 4 v dd v ss v 1 v 3 v 5 cap1+ cap1C cap2+ cap2C cap3C frs fr cl dyo dof m//s segment driver common driver shift register power supply circuit i/o buffer circuit 132 x 65-dot display data ram display data latch line address decoder line counter initial display line register page address register column address decoder 8-bit column address counter 8-bit column address register display timing generator circuit bus holder status register oscillator microprocessor interface i/o buffer coms com s output status selector circuit vs1 cs1 cs2 a0 rd (e) wr (r/w) c86 p/s res d7 (si) d6 (scl) d5 d4 d3 d2 d1 d0 command decoder v out v r
s1d15300 series rev.1.4 epson 5C3 4. pad layout s1d15300 series chips 1 51 52 86 87 137 138 172 die no. chip size: 6.65x4.57 mm pad pitch: 118 m m (min.) s1d1530 * d ** a * (al-pad chip) pad center size: 90x90 m m chip thickness: 300 m m s1d1530 * d ** b * (al-bump chip) bump size: 76x76 m m bump height: 23 m m (typ.) chip thickness: 625 m m
s1d15300 series 5C4 epson rev.1.4 pad pin no. name x y 1 o127 2986 2142 2 o128 2862 3 o129 2738 4 o130 2614 5 o131 2490 6 coms 2366 7 frs 2242 8 fr 2124 9 dyo 2006 10 cl 1888 11 dof 1770 12 vs1 1652 13 m/s 1534 14 res 1416 15 p/s 1298 16 cs1 1180 17 cs2 1062 18 c86 944 19 a0 826 20 wr(w/r) 708 21 rd(e) 590 22 v dd 472 23 d0 354 24 d1 236 25 d2 118 26 d3 0 27 d4 -118 28 d5 -236 29 d6(scl) -354 30 d7(si) -472 31 v ss -590 32 v out -708 33 cap3- -826 34 cap1+ -944 35 cap1- -1062 36 cap2+ -1180 37 cap2- -1298 38 v 5 -1416 39 v r -1534 40 v dd -1652 41 v 1 -1770 42 v 2 -1888 43 v 3 -2006 44 v 4 -2124 45 v 5 -2242 46 o0 -2366 47 o1 -2490 48 o2 -2614 49 o3 -2738 50 o4 -2862 pad pin no. name x y 51 o5 -2986 2142 52 o6 -3178 2006 53 o7 1888 54 o8 1770 55 o9 1652 56 o10 1534 57 o11 1416 58 o12 1298 59 o13 1180 60 o14 1062 61 o15 944 62 o16 826 63 o17 708 64 o18 590 65 o19 472 66 o20 354 67 o21 236 68 o22 118 69 o23 0 70 o24 -118 71 o25 -236 72 o26 -354 73 o27 -472 74 o28 -590 75 o29 -708 76 o30 -826 77 o31 -944 78 o32 -1062 79 o33 -1180 80 o34 -1298 81 o35 -1416 82 o36 -1534 83 o37 -1652 84 o38 -1770 85 o39 -1888 86 o40 -2006 87 o41 -2986 -2142 88 o42 -2862 89 o43 -2738 90 o44 -2614 91 o45 -2490 92 o46 -2366 93 o47 -2242 94 o48 -2124 95 o49 -2006 96 o50 -1888 97 o51 -1770 98 o52 -1652 99 o53 -1534 100 o54 -1416 pad pin no. name x y 101 o55 -1298 -2142 102 o56 -1180 103 o57 -1062 104 o58 -944 105 o59 -826 106 o60 -708 107 o61 -590 108 o62 -472 109 o63 -354 110 o64 -236 111 o65 -118 112 o66 0 113 o67 118 114 o68 236 115 o69 354 116 o70 472 117 o71 590 118 o72 708 119 o73 826 120 o74 944 121 o75 1062 122 o76 1180 123 o77 1298 124 o78 1416 125 o79 1534 126 o80 1652 127 o81 1770 128 o82 1888 129 o83 2006 130 o84 2124 131 o85 2242 132 o86 2366 133 o87 2490 134 o88 2614 135 o89 2738 136 o90 2862 137 o91 2986 138 o92 3178 -2006 139 o93 -1888 140 o94 -1770 141 o95 -1652 142 o96 -1534 143 o97 -1416 144 o98 -1298 145 o99 -1180 146 o100 -1062 147 o101 -944 148 o102 -826 149 o103 -708 150 o104 -590 pad pin no. name x y 151 o105 3178 -472 152 o106 -354 153 o107 -236 154 o108 -118 155 o109 0 156 o110 118 157 o111 236 158 o112 354 159 o113 472 160 o114 590 161 o115 708 162 o116 826 163 o117 944 164 o118 1062 165 o119 1180 166 o120 1298 167 o121 1416 168 o122 1534 169 o123 1652 170 o124 1770 171 o125 1888 172 o126 2006 pad center coordinates unit: m m
s1d15300 series rev.1.4 epson 5C5 5. pin description power supply lcd driver supplies microprocessor interface name i/o description number of pins cap1+ o dc/dc voltage converter capacitor 1 positive connection 1 cap1C o dc/dc voltage converter capacitor 1 negative connection 1 cap2+ o dc/dc voltage converter capacitor 2 positive connection 1 cap2C o dc/dc voltage converter capacitor 2 negative connection 1 cap3C o dc/dc voltage converter capacitor 1 negative connection 1 v out i/o dc/dc voltage converter output 1 vr i voltage adjustment pin. applies voltage between v dd and v5 using 1 a resistive divider. name i/o description number of pins v dd supply +5v power supply. connect to microprocessor power supply pin v cc .2 v ss supply ground 1 v 1 , v 2 supply lcd driver supply voltages. the voltage determined by lcd cell is v 3 , v 4 impedance-converted by a resistive driver or an operational amplifier 6 v 5 for application. voltages should be the following relationship: v dd 3 v 1 3 v 2 3 v 3 3 v 4 3 v 5 when the on-chip operating power circuit is on, the following voltages are given to v 1 to v 4 by the on-chip power circuit. voltage selection is performed by the set lcd bias command. (the s1d15303 and s1d15304 are fixed to 1/5 bias.) s1d15300/s1d15305 s1d15301 s1d15302 v 1 1/5?v 5 1/6?v 5 1/6?v 5 1/8?v 5 1/6?v 5 1/8?v 5 v 2 2/5?v 5 2/6?v 5 2/6?v 5 2/8?v 5 2/6?v 5 2/8?v 5 v 3 3/5?v 5 4/6?v 5 4/6?v 5 6/8?v 5 4/6?v 5 6/8?v 5 v 4 4/5?v 5 5/6?v 5 5/6?v 5 7/8?v 5 5/6?v 5 7/8?v 5 s1d15303 s1d15304 v 1 1/5?v 5 1/5?v 5 v 2 2/5?v 5 2/5?v 5 v 3 3/5?v 5 3/5?v 5 v 4 4/5?v 5 4/5?v 5 name i/o description number of pins d0 to d7 i/o 8-bit bi-directional data bus to be connected to the standard 8-bit or 16-bit 8 microprocessor data bus. (si) when the serial interface selects; (scl) d7: serial data input (si) d6: serial clock input (scl) a0 i control/display data flag input. it is connected to the lsb of micro- 1 processor address bus. when low, the data on d0 to d7 is control data. when high, the data on d0 to d7 is display data. res when res is caused to go low, initialization is executed. 1 a reset operation is performed at the res signal level. cs1 i chip select input. data input/output is enabled when -cs1 is low and 2 cs2 cs2 is high. when chip select is non-active, d0 to d7 will be "hz". rd i ? when interfacing to an 8080 series microprocessor: 1 (e) active low. this input connects the rd signal of the 8080 series microprocessor. while this signal is low, the s1d15300 series data bus output is enabled. ? when interfacing to a 6800 series microprocessor: active high. this is used as an enable clock input pin of the 6800 series microprocessor.
s1d15300 series 5C6 epson rev.1.4 name i/o description number of pins wr i ? write enable input. when interfacing to an 8080-series microprocessor, 1 (r/w) wr is active low. ? when interfacing to an 6800-series microprocessor, it will be read mode when r/w is high and it will be write mode when r/w is low. r/w = 1:read r/w = 0:write c86 i microprocessor interface select terminal. 1 c86 = high: 6800 series microprocessor interface c86 = low: 8080 series microprocessor interface p/s i serial data input/parallel data input select pin. 1 * in serial mode, no data can be read from ram. when p/s = low, d0 to d5 are hz and rd and wr must be fixed high or low. p/s chip select data/command data read/write serial clock high cs1, cs2 a0 d0-d7 rd, wr low cs1, cs2 a0 si(d7) write only scl(d6) lcd driver outputs name i/o description number of pins m/s i s1d15300 series master/slave mode select input. when a necessary 1 signal is output to the lcd, the master operation is synchronized with the lcd system, while when a necessary signal is input to the lcd, the slave operation is synchronized with the lcd system. m/s = high: master operation m/s = low : slave operation the following is provided depending on the m/s status. cl i/o display clock input/output. when the s1d15300 series selects master/ 1 slave mode, each cl pin is connected. when it is used in combination with the common driver, this input/output is connected to common driver yscl pin. m/s = high: output m/s = low: input fr i/o lcd ac signal input/output. when the s1d15300 series selects master/ 1 slave mode, each fr pin is connected. when the s1d15300 series selects master mode this input/output is connected to the common driver fr pin. m/s = high: output m/s = low: input dyo i/o common drive signal output. this output is enabled for only at master 1 operation and connects to the common driver dio pin. it becomes hz at slave operation. vs1 o test pin. dont connect. 1 dof i/o lcd blanking control input/output. when the s1d15300 series selects 1 master/slave mode, the respective dof pin is connected. when it is used in combination with the common driver (s1d16305), this output/ input is connected to the common driver doff pin. m/s = high: output m/s = low: input frs o static drive output. 1 this is enabled only at master operation and used together with the fr pin. this output becomes hz at slave operation. osc power model status supply cl fr dyo frs dof circuit circuit s1d1530 * d **** master enabled enabled output output output output output slave disabled disabled input input hz hz input
s1d15300 series rev.1.4 epson 5C7 name i/o description number of pins on o lcd drive output. the following assignment is made depending on 132 (seg n) the model. (com n) seg output. lcd segment drive output. one of v dd , v 2 , v 3 and v 5 levels is selected by combination of the contents of display ram and fr signal. com output. lcd common drive output. one of v dd , v 1 , v 4 and v 5 levels is selected by combination of scan data and fr signal. coms o indicator com output. when it is not used, it is made open. 1 effective only with the s1d15300, s1d15302, s1d15303 and s1d15304, s1d15305 and hz with the s1d15301. when multiple numbers of the s1d15300, s1d15302, s1d15303 and s1d15304, s1d15305 are used, the same coms signal is output to both master and slave units. total 172 seg com s1d15300d00 ** o0~o99 o100~o131 s1d15300d10 ** o16~o115 o0~o15, o116~o131 s1d15300d15 ** s1d15301d00 ** o0~o131 s1d15302d00 ** o0~o99 o100~o131 s1d15302d14 ** s1d15302d11 ** o32~o131 o0~o31 s1d15303d15 ** o8~o123 o0~o7, o124~o131 s1d15304d14 ** o0~o123 o124~o131 s1d15305d10 ** o18~o115 o0~o17, o116~o131 scan data fr on output voltage high high v 5 low v dd low high v 1 low v 4 power save C v dd ram data fr on output voltage normal display reverse display high high v dd v 2 low v 5 v 3 0 high v 2 v dd low v 3 v 5 power save C v dd
s1d15300 series 5C8 epson rev.1.4 6. functional description microprocessor interface interface type selection the s1d15300 series can transfer data via 8-bit bi-directional data buses (d7 to d0) or via serial data input (si). when high or low is selected for the polarity of p/s pin, either 8-bit parallel data input or serial data input can be selected as shown in table 1. when s erial data input is selected, ram data cannot be read out. table 1 parallel input when the s1d15300 series selects parallel input (p/s = high), the 8080 series microprocessor or 6800 series microprocessor can be selected by causing the c86 pin to go high or low as shown in table 2. table 2 data bus signals the s1d15300 series identifies the data bus signal according to a0, e, r/w, (rd, wr) signals. table 3 serial interface (p/s is low) the serial interface consists of an 8-bit shift register and a 3-bit counter. the serial data input and serial clock input are enabled when cs1 is low and cs2 is high (in chip select status). when chip is not selected, the shift register and counter are reset. serial data of d7, d6, ..., d0 is read at d7 in this sequence when serial clock (scl) goes high. they are converted into 8-bit parallel data and processed on rising edge of every eighth serial clock signal. the serial data input (s1) is determined to be the display data when a0 is high, and it is control data when a0 is low. a0 is read on rising edge of every eighth clock signal. figure 1 shows a timing chart of serial interface signals. the serial clock signal must be terminated correctly against termin ation reflection and ambient noise. operation checkout on the actual machine is recommended. p/s type cs1 cs2 a0 rd wr c86 d7 d6 d0 to d5 high parallel input cs1 cs2 a0 rd wr c86 d7 d6 d0 to d5 low serial input cs1 cs2 a0 C C C si scl (hz) C must always be high or low. common 6800 processor 8080 processor function a0 (r/w) rd wr 1 1 0 1 reads display data. 1 0 1 0 writes display data. 0 1 0 1 reads status. 0 0 1 0 writes control data in internal register. (command) c86 type cs1 cs2 a0 rd wr d0 to d7 high 6800 micro- cs1 cs2 a0 e r/w d0 to d7 processor bus low 8080 micro- cs1 cs2 a0 rd rw d0 to d7 processor bus cs1 scl 1 a0 si cs2 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 2345678910 12 11 d4 d3 d2 d1 14 13 figure 1
s1d15300 series rev.1.4 epson 5C9 chip select inputs the s1d15300 series has two chip select pins, cs1 and cs2 and can interface to a microprocessor when cs1 is low and cs2 is high. when these pins are set to any other combination, d0 to d7 are high impedance and a0, rd and wr inputs are disabled. when serial input interface is selected, the shift register and counter are reset. access to display data ram and internal registers the s1d15300 series can perform a series of pipeline processing between lsis using bus holder of internal data bus in order to match the operating frequency of display ram and internal registers with the microprocessor. for example, the microprocessor reads data from display ram in the first read (dummy) cycle, stores it in bus holder, and outputs it onto system bus in the next data read cycle. also, the microprocessor temporarily stores display data in bus holder, and stores it in display ram until the next data write cycle starts. when viewed from the microprocessor, the s1d15300 series access speed greatly depends on the cycle time rather than access time to the display ram ( t acc ). it shows the data transfer speed to/from the microprocessor can increase. if the cycle time is inappropriate, the microprocessor can insert the nop instruction that is equivalent to the wait cycle setup. however, there is a restriction in the display ram read sequence. when an address is set, the specified address data is not output at the immediately following read instruction. the address data is output during second data read. a single dummy read must be inserted after address setup and after write cycle (refer to figure 2). ?write ?read write signal bus holder internal timing data wr n n mpu n+1 n+2 n+3 latched n+1 n+2 n+3 address preset read signal column address bus holder internal timing preset incremented set address n dummy read data read address n data read address n+1 data rd wr n n n n+1 n n+1 n+2 n n n+1 n+2 mpu figure 2 busy flag the busy flag is set when the s1d15300 series starts to operate. during operating, it accepts read status instruction only. the busy flag signal is output at pin d7 when read status is issued. if the cycle time ( t cyc ) is correct, the microprocessor needs not to check the flag before issuing a command. this can greatly improve the microproc- essor performance. initial display line register when the display ram data is read, the display line according to com0 (usually, the top line of screen) is determined using register data. the register is also used for screen scrolling and page switching. the set display start line command sets the 6-bit display start address in this register. the register data is preset on the line counter each time fr signal status changes. the line counter is incremented by cl signal and it generates a line address to allow 132-bit
s1d15300 series 5C10 epson rev.1.4 column address counter this is a 8 bit presettable counter that provides column address to the display ram (refer to figure 4). it is incremented by 1 when a read/ write command is entered. however, the counter is not incremented but locked if a non-existing address above 84h is specified. it is unlocked when a column address is set again. the column address counter is independent of page address register. when adc select command is issued to display inverse display, the column address decoder inverts the relationship between ram column address and display segment output. page address register this is a 4-bit page address register that provides page address to the display ram (refer to figure 4). the microprocessor issues set page address command to change the page and access to another page. page address 8 (d3 is high, but d2, d1 and d0 are low) is ram area dedicate to the indicator, and display data d0 is only valid. display data ram the display data ram stores pixel data for lcd. it is a 65-column by 132-row (8-page by 8 bit+1) addressable array. each pixel can be selected when page and column addresses are specified. the time required to transfer data is very short because the micro- processor enters d0 to d7 corresponding to lcd common lines as shown in figure 3. therefore, multiple s1d15300 can easily configure a large display having the high flexibility with very few data transmission restriction. the microprocessor writes and reads data to/from the ram through i/o buffer. as lcd controller operates independently, data can be written into ram at the same time as data is being displayed, without causing the lcd to flicker. d0 d1 d2 d3 d4 1 0 1 0 0 com0 com1 com2 com3 com4 display data ram display on lcd figure 3
s1d15300 series rev.1.4 epson 5C11 relationship between display data ram and addresses (if initial display line is 1ch): figure 4 page address data line address com output d3, d2, d1,d0 0,0,0,0 0,0,0,1 0,0,1,0 0,0,1,1 1,0,0,0 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 page 1 page 2 page 3 page 8 00 01 02 03 04 05 06 07 08 09 0a 10 11 12 13 14 15 16 17 18 19 1a 0b 0c 0d 0e 0f 1b 1c 1d 1e 1f com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 coms start column address d0 page 0 0,1,0,1 0,1,1,0 0,1,1,1 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 page 5 page 6 page 7 page 4 0,1,0,0 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f adc d0= "0" d0= "1" lcd out o0 o1 o2 o3 o4 o5 o6 o7 o128 o129 o130 o131 83 82 81 80 7f 7e 7d 7c 03 02 01 00 00 01 02 03 04 05 06 07 80 81 82 83 1/32 1/64 page 8 is accessed during 1/65 or 1/33 duty.
s1d15300 series 5C12 epson rev.1.4 output status selector the s1d15300 series except s1d15301 can set a com output scan direction to reduce restrictions at lcd module assembly. this sc an direction is set by setting 1 or 0 in the output status register d3. fig.5 shows the status. fig. 5 shows the status. the coms pin is assigned to com32 on s1d15300 and it is assigned to com64 on s1d15302 independent from their output status. the coms pin of the s1d15303 is assigned to com16 the coms pin of the s1d15304 is assigned to com8 and the coms pin of the s1d1 5305 is assigned to com34. figure 5 shows the com output pin numbers of s1d15302d00 ** and s1d15302d11 ** in the master mode. in the slave mode, com0 to com31 must be replaced by com32 to com63. display timing generator this section explains how the display timing generator circuit operates. signal generation to line counter and display data latch circuit the display clock (cl) generates a clock to the line counter and a latch signal to the display data latch circuit. the line address of the display ram is generated in synchronization with the display clock. 132-bit display data is latched by the display data latch circuit in synchronization with the display clock and output to the segment lcd drive output pin. the display data is read to the lcd drive circuit completely independent of access to the display data ram from the microproc- essor. lcd ac signal (fr) generation the display clock generates an lcd ac signal (fr). the fr causes the lcd drive circuit to generate a ac drive waveform. it generates a 2-frame ac drive waveform. when the s1d15300 is operated in slave mode on the assumption of multi-chip, the fr pin and cl pin become input pins. common timing signal generation the display clock generates an internal common timing signal and a start signal (dyo) to the common driver. a display clock resulting from frequency division of an oscillation clock is output from the cl pin. when an ac signal (fr) is switched, a high pulse is output as a dyo output at the training edge of the previous display clock. refer to fig. 6. the dyo output is output only in master mode. when the s1d15300 series is used for multi-chip, the slave requires to receive the fr, cl, dof signals from the master. table 4 shows the fr, cl, dyo and dof status. table 4 column address lcd output o0 o131 adc (d0) "0" "1" 0 (h) 83 (h) 83 (h) 0 (h) d3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 s1d15300d00 ]] s1d15300d10 ]] s1d15300d15 ]] s1d15301d00 ]] s1d15302d00 ]] s1d15302d14 ]] s1d15302d11 ]] s1d15303d15 ]] s1d15304d14 ]] s1d15305d10 ]] com15 0 com16 31 com0 com31 com31 com0 seg100 seg100 seg100 seg100 seg132 seg116 seg116 seg124 seg124 seg98 seg98 com16 com15 31 0 com8 com7 com0 com7 com18 com17 15 0 7 0 33 0 display data ram seg100 seg100 com31 com0 0 31 com7 com8 0 15 com17 com16 0 33 seg100 seg100 com0 com31 com31 com0 64 0 1 30 31 64 0 31 32 2 63 12 30 fr (master output) master common slave common 64 32 33 62 63 34 64 model operation fr cl dyo dof mode s1d1530 * d **** master output output output output slave input input hz input hz denotes a high-impedance status.
s1d15300 series rev.1.4 epson 5C13 example of s1d15300d00b * 1/33 duty ? dual-frame ac driver waveforms fig. 6 d2 d1 d0 voltage voltage voltage external voltage voltage booster voltage regulator booster regulator follower input terminal terminal 1 1 1 1 on on on used used 2 0 1 1 off on on v out open used 3 0 0 1 off off on v 5 open open 4 0 0 0 off off off v 1 to v 5 open open display data latch circuit. this circuit temporarily stores (or latches) display data (during a single common signal period) when it is output from display ram to lcd panel driver circuit. this latch is controlled by display in normal/in reverse display on/off and static all-display on com- mands. these commands do not alter the data. lcd driver this is a multiplexer circuit consisting of 133 segment outputs to generate four-level lcd panel drive signals. the lcd panel drive voltage is generated by a specific combination of display data, com scan signal, and fr signal. figure 8 gives an example of seg and com output waveforms. oscillator circuit this is an oscillator having a complete built-in type cr, and its output is used as the display timing signal source or as the clock for voltage booster circuit of the lcd power supply. the oscillator circuit is available in master mode only. the oscillator signal is divided and output as display clock at cl pin. power supply circuit the power supply circuit generates voltage to drive the lcd panel at low power consumption, and is available in s1d15300 master mode only. the power supply circuit consists of a voltage booster voltage regulator, and lcd drive voltage follower. the power supply circuit built in the s1d15300 series is set for a small-scale lcd panel and is inappropriate to a large-pixel panel and a large-display-capacity lcd panel using multiple chips. as the large lcd panel has the dropped display quality due to a large load capacity, it must use an external power source. the power circuit is controlled by set power control command. this command sets a three-bit data in power control register to select one of eight power circuit functions. the external power supply and part of internal power circuit functions can be used simultaneously. the following explains how the set power control command works. [control by set power control command] d2 turns on when triple booster control bit goes high, and d2 turns off when this bit goes low. d1 turns on when voltage regulator control bit goes high, and d1 turns off when this bit goes low. d0 turns on when voltage follower control bit goes high, and d0 turns off when this bit goes low. [practical combination examples] status 1: to use only the internal power supply. status 2: to use only the voltage regulator and voltage follower. status 3: to use only the voltage follower. input the external voltage as v 5 =vout. status 4: to use only an external power supply because the internal power supply does not operate. * the voltage booster terminals are cap1+, cap1-, cap2+, cap2- and cap3-. * combinations other than those shown in the above table are possible but impractical. 3233123456 28293031323312 v dd v1 v4 v5 v1 v4 v5 com1 cl com0 fr ram data segn dyo v dd v dd v2 v3 v5 345
s1d15300 series 5C14 epson rev.1.4 booster circuit if capacitors c1 are inserted between cap1+ and cap1-, between cap2+ and cap2-, cap1+ and cap3- and vss and vout, the potential between vdd and vss is boosted to quadruple toward the negative side and it is output at vout. for triple boosting, remove only capacitor c1 between cap+1 and cap3- from the connection of quadruple boosting operation and jumper between cap3- and vout. the triple boosted voltage appears at vout (cap3-). for double boosting, remove only capacitor c1 between cap2+ and cap2- from the connection of triple boosting operation, open cap+2 and jumper between cap2- and vout (cap3-). the double boosted voltage appears at vout (cap3-, cap2-). for quadruple boosting, set a vss voltage range so that the voltage at vout may not exceed the absolute maximum rating. as the booster circuit uses signals from the oscillator circuit, the oscillator circuit must operate. subsection 10.1.1 gives an external wiring example to use master and slave chips when on-board power supply is active. v reg is the constant voltage source of the ic, and in case of type 1, it is constant and v reg C2.55 v (if v dd is 0 v), in case of type 2, v reg =v ss (v dd basis). to adjust the v 5 output voltage, insert a variable resistor between v r , v dd and v 5 as shown. a combination of r1 and r3 constant resistors and r2 variable resistor is recommended for fine-adjustment of v 5 voltage. setup example of resistors r1, r2 and r3: when the electronic volume control function is off (electronic volume control register values are (d4,d3,d2,d1,d0)=(0,0,0,0,0)): v 5 = v reg ....................... 1 (as i ref = 0 a) r1 + r2 + r3 = 5m w ................................ 2 (determined by the current passing between v dd and v 5 ) variable voltage range by r2 v 5 = ? to ?0 v (determined by the lcd characteristics) d r2 = o w , v reg = e2.55v to obtain v 5 = -10 v, from equation 1 : r2 + r3 = 2.92 r1 ..................... 3 d r2 = r2, v reg = e2.55v to obtain v 5 = -6 v, from equation 1 : 1.35 (r1 + r2) = r3 .................. 4 from equations 2 , 3 and 4 : r1=1.27m w r2=0.85m w r3=2.88m w the voltage regulator circuit has a temperature gradient of approximately -0.2%/ c as the v reg voltage. to obtain another temperature gradient, use the electronic volume control function for software processing using the mpu. as the v r pin has a high input impedance, the shielded and short lines must be protected from a noise interference. voltage regulator using the electronic volume control function the electronic volume control function can adjust the intensity (brightness level) of liquid crystal display (lcd) screen by command control of v 5 lcd driver voltage. this function sets five-bit data in the electronic volume control register, and the v 5 lcd driver voltage can be one of 32-state voltages. to use the electronic volume control function, issue the set power control command to simultaneously operate both the voltage regulator circuit and voltage follower circuit. also, when the boosting circuit is off, the voltage must be supplied from v out terminal. when the electronic volume control function is used, the v 5 voltage can be expressed as follows: v 5 = (1 + ) v reg + rb d i ref ........................ 5 variable voltage range the increased v 5 voltage is controlled by use of i ref current source of the ic. (for 32 voltage levels, d i ref = i ref /31) (v =+5v) v =0v cc dd (gnd) v =-5v ss v =2v =-10v ss out potential during double boosting v =0v dd v =-3v ss v =3v =-12v ss out potential during quadruple boosting v =0v dd v =-5v ss v =3v =-15v ss out potential during triple boosting voltage regulator circuit the boosting voltage occurring at v out is sent to the voltage regulator and the v 5 liquid crystal display (lcd) driver voltage is output. this v 5 voltage can be determined by the following equation when resistors ra and rb (r1, r2 and r3) are adjusted within the range of |v5| < |v out |. v dd v reg r1 + - v 5 =(1+ ) v reg +i ref rb ra r2 d r2 vr i ref =(1+ ) v reg r1+ d r2 r3+r2- d r2 +i ref (r3+r2- d r2) rb v 5 r3 ra rb ( 1 + r3 + r2 e d r2) r1 + d r2 rb ra . = .
s1d15300 series rev.1.4 epson 5C15 the minimum setup voltage of the v 5 absolute value is determined by the ratio of external ra and rb, and the increased voltage by the electronic volume control function is determined by resistor rb. therefore, the resistors must be set as follows: 1) determine rb resistor depending on the v 5 variable voltage range by use of the electronic volume control. rb = v 5 variable voltage range i ref 2) to obtain the minimum voltage of the v 5 absolute value, determine ra using the rb of step 1) above. ra = rb v 5 C1 {v 5 = (1 + rb/ra) v reg } v reg the s1d15300 series have the built-in v reg reference voltage and i ref current source which are constant during voltage variation. however, they may change due to the variation occurring in ic manufacturing and due to the temperature change as shown below. consider such variation and temperature change, and set the ra and rb appropriate to the lcd used. v reg = e2.55v 0.20v (type1) v reg = e0.2%/?c v reg = v ss (v dd basis) (type2) v reg = e0.00%/?c i ref = e3.2 m a 40% (for 16 levels) i ref = 0.023 m a/ c e6.5 m a 40% (for 32 levels) 0.052 m a/ c ra is a variable resistor that is used to correct the v 5 voltage change due to v reg and i ref variation. also, the contrast adjustment is recommended for each ic chip. before adjusting the lcd screen contrast, set the electronic volume control register values to (d4,d3,d2,d1,d0)=(1,0,0,0,0) or (0,1,1,1,1) first. when not using the electronic volume control function, set the register values to (d4,d3,d2,d1,d0)=(0,0,0,0,0) by sending the res signal or the set electronic volume control register command. setup example of constants when electronic volume control function is used: v 5 maximum voltage: v 5 = e6 v (electronic volume control register values (d4,d3,d2,d1,d0) = (0,0,0,0,0)) v 5 minimum voltages: v 5 = e10 v (electronic volume control register values (d4,d3,d2,d1,d0) = (1,1,1,1,1)) v 5 variable voltage range: 4 v variable voltage levels: 32 levels 1) determining the rb: r3 = v 5 variable voltage range = 4v | i ref | 6.5 m a rb = 625k w 2) determining the ra: ra = rb = 625k w v 5 max e1 e6v e1 v reg e2.55v ra = 462k w ta=25 c v 5 max = (1+rb/ra) v reg = (1+625k/442k) (e2.55v) = e6.0v v 5 min = v 5 max + rb i ref = e6v + 625k (e6.5 m a) = e10.0v s1d15300 series v 5 [v] -10v -5v -20 0 20 40 60 ta [?c] v 5 variable voltage range (32 levels) v 5 (v dd ) 0v according to the v 5 voltage and temperature change, equation 5 can be as follows (if v dd = 0 v reference): ta=?0 c v 5 max = (1+rb/ra) v reg (ta=e10 c) = (1+625k/462k) (e2.55v) {1+(e0.2%/ c) (e10 ce25 c)} = e6.42v v 5 min = v 5 max + rb i ref (ta=e10 c) = e6.42v + 625k {e6.5 m a+(0.052 m a/ c) (e10 ce25 c)} = e11.63v ta=e50 c v 5 max = (1+rb/ra) v reg (ta=50 c) = (1+625k/462k) (e2.55v) {1+(e0.2%/ c) (50 ce25 c)} = e5.7v v 5 min = v 5 max + rb i ref (ta=50 c) = e5.7v + 625k {e6.5 m a+(0.052 m a/ c) (50 ce25 c)} = e8.95v the margin must also be determined in the same procedure given above by considering the v reg and i ref variation. this margin calculation results show that the v 5 center value is affected by the v reg and i ref variation. the voltage setup width of the electronic volume control depends on the i ref variation. when the typical value of 0.2 v/step is set, for example, the maximum variation range of 0.12 to 0.28 v must be considered. in case of type 2, it so becomes that v reg = v ss (v dd basis) and there is no temperature gradient. however, i ref carries the same temperature characteristics as with type 1. command sequence when built-in power supply is turned off to turn off the built-in power supply, follow the command sequence as shown below to turn it off after making the system into the standby mode. built-in power off static indicator on display off command adh command a5h command aeh power save command entire displays on
s1d15300 series 5C16 epson rev.1.4 voltage generator circuit 1 e1 power set command 1 e2 when the on-chip power circuit is used 2 when v out is input from the outside when the built-in power supply (d2, d1, d0) = (0, 1, 1) is used (triple boosting) (d2, d1, d0) = (1, 1, 1) 3 when v 5 is input from the outside 4 when the on-chip power circuit is used (d2, d1, d0) = (0, 0, 1) v ss cap3- cap1+ cap1- cap2+ cap2- v out v 5 v r r3 r2 v dd r1 v 1 v 2 v 3 v 4 v 5 c2 m/s v dd s1d15300 series v ss cap3- cap1+ cap1- cap2+ cap2- v out v 5 v r v 1 v 2 v 3 v 4 v 5 m/s v dd s1d15300 series v ss v ss v ss v ss external power supply c1 c1 c1 r3 r2 v dd r1 c2 v dd v dd c1 v ss cap3- cap1+ cap1- cap2+ cap2- v out v 5 v r r3 r2 v dd r1 v 1 v 2 v 3 v 4 v 5 c2 m/s cl cl v dd s1d15300 series v ss c1 c1 c1 v dd v ss cap3- cap1+ cap1- cap2+ cap2- v out v 5 v r v 1 v 2 v 3 v 4 v 5 m/s cl v dd s1d15300 series v ss v ss external power supply v dd c2 v dd v ss cap3- cap1+ cap1- cap2+ cap2- v out v 5 v r v dd v 1 v 2 v 3 v 4 v 5 m/s v dd s1d15300 series v ss external power supply v dd
s1d15300 series rev.1.4 epson 5C17 reference setup value: s1d15300 v 5 = -7 to -9 v s1d15301 v 5 = -11 to -13 v (variable) s1d15302 v 5 = -11 to -13 v (variable) sed1530 sed1531 sed1532 c1 1.0~4.7 uf 1.0~4.7 uf 1.0~4.7 uf c2 0.22~0.47 uf 0.47~1.0 uf 0.47~1.0 uf r1 700 k w 1 m w 1 m w r2 200 k w 200 k w 200 k w r3 1.6 m w 4 m w 4 m w lcd 16 50 mm 32 64 mm 32 100 mm size dot 32 100 64 128 64 200 configuration reset circuit when the res input goes low, this lsi is initialized. initialized status 1. display off 2. normal display 3. adc select: normal display (adc command d0 = low) 4. read modify write off 5. power control register (d2, d1, d0) = (0, 0, 0) 6. register data clear in serial interface 7. lcd power supply bias ratio 1/6 (s1d15300), 1/8 (s1d15301, se1d15302) 8. static indicator: off 9. display start line register set at line 1 10. column address counter set at address 0 11. page address register set at page 0 12. output status register (d3) = (0) 13. electronic control register set at 0 14. test command off as seen in 11. microprocessor interface (reference example), connect the res pin to the reset pin of the microprocessor and initialize the microprocessor at the same time. in case the s1d15300 series does not use the internal lcd power supply circuit, the res must be low when the external lcd power supply is turned on. when res goes low, each register is cleared and set to the above initialized status. however, it has no effect on the oscillator circuit and output pins (fr, cl, dyo, d0 to d7). the initialization by res pin signal is always required during power-on. if the control signal from the mpu is hz, an overcurrent may flow through the ic. a protection is required to prevent the hz signal at the input pin during power-on. be sure to initialize it by res pin when turning on the power supply. when the reset command is used, only parameters 8 to 14 in the above initialization are executed. 1: as the input impedance of v r is high, a noise protection using short wire and cable shield is required. *2: c1 and c2 depend on the capacity of the lcd panel to be driven. set a value so that the lcd drive voltage may be stable. [setup example] turn on the voltage regulator and voltage follower and give an external voltage to v out . display a horizontal-stripe lcd heavy load pattern and determine c2 so that the lcd drive voltage (v 1 to v 5 ) may be stable. however, the capacity value of c2 must be all equal. next, turn on all the on-board power supplies and determine c1. *3: lcd size means the length and breadth of the display portion of the lcd panel. model lcd drive voltage s1d15300 1/5 or 1/6 bias s1d15301 1/6 or 1/8 bias s1d15302 * precautions when installing the cog when installing the cog, it is necessary to duly consider the fact that there exists a resistance of the ito wiring occurring between the driver chip and the externally connected parts (such as capacitors and resistors). by the influence of this resistance, non-conformity may occur with the indications on the liquid crystal display. therefore, when installing the cog design the module paying sufficient considerations to the following three points. 1. suppress the resistance occurring between the driver chip pin to the externally connected parts as much as possible. 2. suppress the resistance connecting to the power supply pin of the driver chip. 3. make various cog module samples with different ito sheet resistance to select the module with the sheet resistance with sufficient operation margin. also, as for this driver ic, pay sufficient attention to the following points when connecting to external parts for the characteristics of the circuit. 1. connection to the boosting capacitors the boosting capacitors (the capacitors connecting to respective cap pins and capacitor being inserted between v out and v ss2 ) of this ic are being switched over by use of the transistor with very low on- resistance of about 10 w . however, when installing the cog, the resistance of ito wiring is being inserted in series with the switching transistor, thus dominating the boosting ability. consequently, the boosting ability will be hindered as a result and pay sufficient attention to the wiring to respective boosting capacitors. 2. connection of the smoothing capacitors for the liquid crystal drive the smoothing capacitors for the liquid crystal driving potentials (v 1 . v 2 , v 3 and v 4 ) are indispensable for liquid crystal drives not only for the purpose of mere stabilization of the voltage levels. if the ito wiring resistance which occurs pursuant to installation of the cog is supplemented to these smoothing capacitors, the liquid crystal driving potentials become unstable to cause non-conformity with the indications of the liquid crystal display. therefore, when using the cog module, we definitely recommend to connect reinforcing resistors externally. reference value of the resistance is 100k w to 1m w . meanwhile, because of the existence of these reinforcing resistors, current consumption will increase. indicated below is an exemplary connection diagram of external resistors. please make sufficient evaluation work for the display statuses with any connection tests.
s1d15300 series 5C18 epson rev.1.4 com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 com 0 v dd v 1 v 2 v 3 v 4 v 5 fr v dd v ss com 1 v dd v 1 v 2 v 3 v 4 v 5 com 2 v dd v 1 v 2 v 3 v 4 v 5 seg 0 v dd v 1 v 2 v 3 v 4 v 5 seg 1 v dd v 1 v 2 v 3 v 4 v 5 com -seg 0 v 5 v 4 v 3 v 2 v 1 v dd -v 1 -v 2 -v 3 -v 4 -v 5 com -seg 1 v 5 v 4 v 3 v 2 v 1 v dd -v 1 -v 2 -v 3 -v 4 -v 5 figure 8 exemplary connection diagram 1. exemplary connection diagram 2. v dd v dd v 1 v 2 v 3 v 4 v 5 r 4 r 4 r 4 r 4 c 2 c 2 s1d15300 series c 2 c 2 c 2 v dd v dd v 1 v 2 v 3 v 4 v 5 r 4 r 4 c 2 c 2 s1d15300 series c 2 c 2 c 2
s1d15300 series rev.1.4 epson 5C19 (4) set column address specifies column address of display ram. divide the column address into 4 higher bits and 4 lower bits. set each of them succession. when the microprocessor repeats to access to the display ram, the column address counter is incremented by 1 during each access until address 132 is accessed. the page address is not changed during this time. (5) read status busy: when high, the s1d15206 series is busy due to internal operation or reset. any command is rejected until busy goes low. the busy check is not required if enough time is provided for each cycle. adc: indicates the relationship between ram column address and segment drivers. when low, the display is normal and column address 131-n corresponds to segment driver n. when high, the display is reversed and column address n corresponds to segment driver n. on/off: indicates whether the display is on or off. when goes low, the display turns on. when goes high, the display turns off. this is the opposite of display on/off command. reset: indicates the initialization is in progress by res signal or by reset command. when low, the display is on. when high, the chip is being reset. (6) write display data writes 8-bit data in display ram. as the column address is incremented by 1 automatically after each write, the microproc- essor can continue to write data of multiple words. 7. commands the s1d15300 series uses a combination of a0, rd (e) and wr (r/ w) signals to identify data bus signals. as the chip analyzes and executes each command using internal timing clock only regardless of external clock, its processing speed is very high and its busy check is usually not required. the 8080 series microprocessor interface enters a read status when a low pulse is input to the rd pin and a write status when a low pulse is input to the wr pin. the 6800 series microprocessor interface enters a read status when a high pulse is input to the r/w pin and a write status when a low pulse is input to this pin. when a high pulse is input to the e pin, the command is activated. (for timing, see timing characteristics.) accordingly, in the command explanation and command table, rd (e) becomes 1 (high) when the 6800 series microprocessor interface reads status or display data. this is an only different point from the 8080 series microprocessor interface. taking the 8080 series microprocessor interface as an example, commands will be explained below. when the serial interface is selected, input data starting from d7 in sequence. (1) display on/off alternatively turns the display on and off. the display turns off when d goes low, and it turns on when d goes high. (2) start display line specifies line address (refer to figure 4) to determine the initial display line, or com0. the ram display data becomes the top line of lcd screen. it is followed by the higher number of lines in ascending order, corresponding to the duty cycle. when this command changes the line address, the smooth scrolling or page change takes place. (3) set page address specifies page address to load display ram data to page address register. any ram data bit can be accessed when its page address and column address are specified. the display remains unchanged even when the page address is changed. page address 8 is the display ram area dedicate to the indica- tor, and only d0 is valid for data change. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010111d e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 1 a5a4a3a2a1a0 ? high-order bit a5 a4 a3 a2 a1 a0 line address 000000 0 000001 1 000010 2 :: 111110 6 2 111111 6 3 a3 a2 a1 a0 page address 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101011a3a2a1a0 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 higher bits 0100001a7a6a5a4 lower bits 0100000a3a2a1a0 a7 a6 a5 a4 a3 a2 a1 a0 column address 00000000 0 00000001 1 :: 10000011 1 3 1 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 001 busy adc on/off reset 0000 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 write data
s1d15300 series 5C20 epson rev.1.4 (7) read display data reads 8-bit data from display ram area specified by column address and page address. as the column address is incremented by 1 automatically after each write, the microprocessor can continue to read data of multiple words. a single dummy read is required immediately after column address setup. refer to the display ram section of functional description for details. note that no display data can be read via the serial interface. (8) adc select changes the relationship between ram column address and segment driver. the order of segment driver output pins can be reversed by software. this allows flexible ic layout during lcd module assembly. for details, refer to the column address section of figure 4. when display data is written or read, the column address is incremented by 1 as shown in figure 4. when d is low, the right rotation (normal direction). when d is high, the left rotation (reverse direction). (9) normal/reverse display reverses the display on/off status without rewriting the contents of the display data ram. when d is low, the ram data is high, being lcd on potential (normal display). when d is high, the ram data is low, being lcd on potential (reverse display). (10) entire display on forcibly turns the entire display on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this command has priority over the normal/reverse display command. when d is low, the normal display status is pro- vided. when d is high, the entire display on status is provided. if the entire display on command is executed in the display off status, the lcd panel enters power save mode. refer to the power save section for details. (11) set lcd bias selects a bias ratio of the voltage required for driving the lcd. this command is enabled when the voltage follower in the power supply circuit operates. (the lcd bias setting command is invalid for the s1d15303 and s1d15304. they are being fixed to the 1/5 bias.) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 read data e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010000d e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010011d e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010010d e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010001d (12) read-modify-write a pair of read-modify-write and end commands must always be used. once read-modify-write is issued, column address is not incremented by read display data command but incremented by write display data command only. it contin- ues until end command is issued. when the end is issued, column address returns to the address when read-modify- write was issued. this can reduce the microprocessor load when data of a specific display area is repeatedly changed during cursor blinking or others. note: any command except read/write display data and set column address can be issued during read-modify-write mode. ? cursor display sequence the potential v 5 is resistively divided inside the ic to produce potentials v 1 , v 2 , v 3 and v 4 which are necessary to drive the lcd. the bias ratio can be selected using the lcd bias setting command. (the s1d15303 and s1d15304 are fixed to 1/5 bias.) moreover, the potentials v 1 , v 2 , v 3 and v 4 are converted in the impedance and supplied to the lcd drive circuit. model bias ratio of lcd power supply s1d15300 1/5 bias or 1/6 bias s1d15301 1/6 bias or 1/8 bias s1d15302 s1d15303 1/5 bias s1d15304 set page address set column address read-modify-write dummy read read data write data completed? end no yes e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100000
s1d15300 series rev.1.4 epson 5C21 (13) end cancels read-modify-write mode and returns column address to the original address (when read-modify-write was issued). (14) reset resets the initial display line register, column address coun- ter, page address register, and output status selector circuit to their initial status. the reset command does not affect on the contents of display ram. refer to the reset circuit section of functional description. the reset command cannot initialize lcd power supply. only the reset siganl to the res pin can initialize the supplies. (15) output status select register applicable to the s1d15300 and s1d15302. when d is high or low, the scan direction of the com output pin is selectable. refer to output status selector circuit in functional descrip- tion for details. d: selects the scan direction of com output pin * : invalid bit (16) set power control selects one of eight power circuit functions using 3-bit register. an external power supply and part of on-chip power circuit can be used simultaneously. refer to power supply circuit section of functional description for details. when a0 goes low, voltage follower turns off. when a0 goes high, it turns on. when a1 goes low, voltage regulator turns off. when a1 goes high, it turns on. when a2 goes low, voltage booster turns off. when a2 goes high, it turns on. (17) set electronic control adjusts the contrast of lcd panel display by changing v5 lcd drive voltage that is output by voltage regulator of on-board power supply. this command selects one of 32 v 5 lcd drive voltages by storing data in 5-bit register. the v 5 voltage adjusting range should be determined depending on the external resistance. refer to the voltage regulator section of functional description for details. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011101110 column address read-modify-write mode is selected. end return n n+1 n+2 n+3 n+m n d4 d3 d2 d1 d0 | v5 | 00000 low 00001 00010 : 11101 11110 1 1 1 1 1 high e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100010 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101100d *** e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01000101a2a1a0 r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 0 a4 a3 a2 a1 a0 set register to (d4,d3,d2,d1,d0)=(0,0,0,0,0) to suppress elec- tronic control function. (18) static indicator this command turns on or off static drive indicators. the indicator display is controlled by this command only, and it is not affected by the other display control commands. either fr or frs terminal is connected to either of static indicator lcd drive electrodes, and the remaining terminal is connected to another electrode. when the indicator is turned on, the static drive operates and the indicator blinks at an interval of approximately one second. the pattern separation between indicator electrodes are dynamic drive electrodes is recommended. a closer pattern may cause an lcd and electrode deterioration. d 0: static indicator off 1: static indicator on (19) power save (compound command) when all displays are turned on during indicator off, the power save command is issued to greatly reduce the current consump- tion. if the static indicators are off, the power save command sleeps the system. if on, this command stands by the system. release the sleep mode using the both power save off command (indicator on command or all indicator displays off command) and static indictor on command. release the standby mode using the power save off command (indicator on command or all indicator displays off command). e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010110d static off indicator on power save (compound command) (sleep mode) (standby mode) (sleeve mode released) (standby mode released) power save off (display on command or entire displays off command) static indicator on
s1d15300 series 5C22 epson rev.1.4 sleep mode this mode stops every operation of the lcd display system, and can reduce current consumption nearly to a static current value if no access is made from the microprocessor. the internal status in the sleep mode is as follows: (1) stops the oscillator circuit and lcd power supply circuit. (2) stops the lcd drive and outputs the vdd level as the segment/common driver output. (3) holds the display data and operation mode provided before the start of the sleep mode. (4) the mpu can access to the built-in display ram. standby mode stops the operation of the duty lcd display system and turns on only the static drive system to reduce current consumption to the minimum level required for static drive. the on operation of the static drive system indicates that the s1d15300 series is in the standby mode. the internal status in the standby mode is as follows: (1) stops the lcd power supply circuit. (2) stops the lcd drive and outputs the vdd level as the segment/common driver output. however, the static drive system operates. (3) holds the display data and operation mode provided before the start of the standby mode. (4) the mpu can access to the built-in display ram. when the reset command is issued in the standby mode, the sleep mode is set. when the lcd drive voltage level is given by an external resistive driver, the current of this resistor must be cut so that it may be fixed to floating or v dd level, prior to or concurrently with causing the s1d15300 series to go to the sleep mode or standby mode. when an external power supply is used, likewise, the function of this external power supply must be stopped so that it may be fixed to floating or v dd level, prior to or concurrently with causing the s1d15300 series to go to the sleep mode or standby mode. when the common driver s1d16305 or s1d16501 is combined with the s1d15301 in the configuration, the dof pin of the s1d15301 must be connected to the doff pin of the s1d16305 or s1d16501. (20) test command this is the dedicate ic chip test command. it must not be used for normal operation. if the test command is issued errone- ously, set the -res input to low or issue the reset command to release the test mode. * : invalid bit cautions: the s1d15300 series holds an operation status specified by each command. however, the internal operation status may be changed by a high level of ambient noise. it must be considered to suppress the noise on the its package and system or to prevent an ambient noise insertion. to prevent a spike noise, a built-in software for periodical status refreshment is recommended to use. the test command can be inserted in an unexpected place. therefore, it is recommended to enter the test mode reset command f0h during the refresh sequence. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101111 ****
s1d15300 series rev.1.4 epson 5C23 command code function a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 (1) display on/off 0 1 0 1 0 1 0 1 1 1 0 turns on lcd panel when goes 1 high, and turns off when goes low. (2) initial display line 0 1 0 0 1 start display address specifies ram display line for com0. (3) set page address 0 1 0 1 0 1 1 page address sets the display ram page in page address register. (4) set column address 0 1 0 0 0 0 1 higher column sets 4 higher bits of column 4 higher bits address address of display ram in register (4) set column address 0 1 0 0 0 0 0 lower column sets 4 lower bits of column 4 lower bits address address of display ram in register (5) read status 0 0 1 status 0 0 0 0 reads the status information. (6) write display data 1 1 0 write data writes data in display ram. (7) read display data 1 0 1 read data reads data from display ram. (8) adc select 0 1 0 1 0 1 0 0 0 0 0 sets normal relationship between 1 ram column address and seg- ment driver when low, but re- verses the relationship when high. (9) normal/reverse display 0 1 0 1 0 1 0 0 1 1 0 normal indication when low, but 1 full indication when high. (10) entire display on/off 0 1 0 1 0 1 0 0 1 0 0 selects normal display (0) or 1 entire display on (1). (11) set lcd bias 0 1 0 1 0 1 0 0 0 1 0 sets lcd drive voltage bias ratio. 1 (12) read-modify-write 0 1 0 1 1 1 0 0 0 0 0 increments column address counter during each write when high and during each read when low. (13) end 0 1 0 1 1 1 0 1 1 1 0 releases the read-modify-write. (14) reset 0 1 0 1 1 1 0 0 0 1 0 resets internal functions. (15) set output status 0 1 0 1 1 0 0 0 * * * selects com output scan register 1 direction. * invalid data (16) set power control 0 1 0 0 0 1 0 1 operation selects the power circuit status operation mode. (17) set electronic control 0 1 0 1 0 0 electronic control value sets v5 output voltage to elec- register tronic control register. (18) set standby 0 1 0 1 0 1 0 1 1 0 0 selects standby status. 1 0: off 1: on (19) power save C C C C C C C C C C C compound command of display off and entire display on (20) test command 0 1 0 1 1 1 1 * * * * ic test command. do not use! (21) test mode reset 0 1 0 1 1 1 1 0 0 0 0 command of test mode reset note: do not use any other command, or the system malfunction may result.
s1d15300 series 5C24 epson rev.1.4 8. command setting (for refrence) instruction setup examples initial setup note: as power is turned on, this ic outputs non-lcd-drive potentials v 2 C v 6 from seg terminal (generates output for driving the lcd) and v 1 C v 4 from com terminal (also used for generating the lcd drive output). if charge remains on the smoothing capacitor being inserted between the above lcd driving terminals, the display screen can be blacked out momentarily. in order to avoid this tr ouble, it is recommended to employ the following powering on procedure. ? when the built-in power is used immediately after the main power is turned on: turn on v dd and v ss power while maintaining res terminal at low. wait until the power supply is stabilized. turn on the initial setup mode (default). *1 initial setup is complete function select through the commands (user setup). lcd bias set *2 adc select *3 common output mode select *4 function select through the command (user setup). electronic volume *5 function select through the command (user setup) power control set *6 cancel the reset mode (res terminal = high). operations ranging from powering on through the power control set must be completed within 5 ms. * this duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned. notes: *1: refer to the reset circuit in the function description. *2: refer to the lcd bias set in the command description (11). *3: refer to the adc select in the command description (8). *4: refer to the output state register set in the command description (15) *5: refer to the supply circuit in the function description and the electronic volume register set in the command descriptio n (17). *6: refer to the supply circuit in the function description and the power control set in the command description (16).
s1d15300 series rev.1.4 epson 5C25 ? when the built-in power supply is not used immediately after the main power is turned on: turn on the power save mode (multiple commands) *7 turn v dd and v ss power on with res terminal being set to low. wait until the power supply is stabilized. turn on the initial setup mode (default) *1 initial setup is complete function select through the commands (user setup) lcd bias set *2 adc select *3 common output mode select *4 function select through the command (user setup) electronic volume *5 turn off the power save mode *6 function select through the command (user setup) power control set * 7 cancel the reset mode (res terminal = high) operations ranging from turning off of the power save mode through the power control set must be completed within 5 ms. the power save mode must be turned on within 5 ms from powering on. * this duration of 5 ms depends on the panel characteristics as well as capacity of the capacitor concerned. check them on the actual system. notes: *1: refer to the reset circuit in the function description. *2: refer to the lcd bias set in the command description (11). *3: refer to the adc select in the command description (8). *4: refer to the output state register set in the command description (15) *5: refer to the supply circuit in the function description and the electronic volume register set in the command descriptio n (17). *6: refer to the supply circuit in the function description and the power control set in the command description (16). *7: you can select either the sleep mode or standby mode for the power save mode. refer to the power save (multiple commands) in the command description (19).
s1d15300 series 5C26 epson rev.1.4 ? data display data display is complete initial setup is complete function select through the commands (user setup) display start line set *8 page address set *9 column address set *10 function select through the command (user setup) display on/off *12 function select through the command (user setup) display data write *11 notes: *8: refer to the display line set in the command description (2). *9: refer to the page address set in the command description (3). *10: refer to the column address set in the command description (4). *11: refer to the display data write in the command description (6). *12: refer to the display on/off in the command description (1). it is recommended to avoid the all-white-display of the disp lay start data. ? powering off *13 turn v dd and v ss power off any state function select through the command (user setup) power save *14 the time spent for the operations ranging from power save through powering off (v dd C v ss = 2.4v) ( t h ) must be longer than the time required for v 5 to v 1 go under the lcd panel threshold voltage (normally 1v). * t h is determined by time constant of the external resisters ra and rb (for adjusting voltages v 5 to v 1 ) and the smoothing capacitor c2. * it is recommended to cut t h shorter by connecting a resistor between v dd and v 5 . notes: *13: this ic functions as the logic circuit of the power supplies v dd C v ss , and used for controlling the driver of lcd power supplies v dd C v 5 . thus, if power supplies v dd C v ss are turned off while voltage is still present on lcd power supplies v dd C v 5 , drivers (com and seg) may output uncontrolled voltage. therefore, you are required to observe the following powering off procedure: turn the built-in power supply off, then turn off the ic power supplies (v dd C v ss ) only after making sure that potential of v 5 C v 1 is below the lcd panel threshold voltage level. refer to the supply circuit in the function description. *14: when the power save command is entered, you must not implement reset from res terminal until v dd C v ss power are turned off. refer to the power save in the command description. ? refresh it is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of unexpected n oise. cancel the test mode *15 refresh sequence refresh the ddram. set every command according to the state being selected (including setup of the default state). notes: *15: refer to the test mode cancellation in the command description (21).
s1d15300 series rev.1.4 epson 5C27 9. absolute maximum ratings notes: 1. v 1 to v 5 , v out , voltages are based on v dd =0 v. 2. voltages v dd v 1 v 2 v 3 v 4 v 5 must always be satisfied. 3. if an lsi exceeds its absolute maximum rating, it may be damaged permanently. it is desirable to use it under electrical cha racteristics conditions during general operation. otherwise, an lsi malfunction or reduced lsi reliability may result. parameter symbol rating unit C0.3 to +7.0 supply voltage range triple boosting v dd C0.3 to +6.0 v quadruple boosting C0.3 to +4.5 supply voltage range (1) (v dd level) v 5 , v out C18.0 to +0.3 v supply voltage range (2) (v dd level) v 1 , v 2 , v 3 , v 4 v 5 to +0.3 v input voltage range v in C0.3 to v dd +0.3 v output voltage range v o C0.3 to v dd +0.3 v operating temperature range t opr C40 to +85 c storage temperature range tcp t str C55 to +100 c bear chip C55 to +125 v dd v ss v dd v , v out (s1d15300 series) (system) v cc gnd v to v 5 14
s1d15300 series 5C28 epson rev.1.4 10. electrical characteristics dc characteristics v ss = 0 v, v dd = 5 v 10%, ta = C40 to +85 c unless otherwise noted. item symbol condition min. typ. max. unit pin used power voltage (1) v dd 4.5 5.0 5.5 v v ss *1 operational 2.4 C 6.0 operating voltage operational v 5 v dd level (v dd = 0 v) C16.0 C C4.5 v v 5 *2 (2) operational v 1 , v 2 v dd level (v dd = 0 v) 0.4 v 5 Cv dd vv 1 , v 2 operational v 3 , v 4 v dd level (v dd = 0 v) v 5 C 0.6 v 5 vv 3 , v 4 high-level input voltage v ihc 0.7 v dd Cv dd v*3 v dd = 2.7 v 0.8 v dd Cv dd *3 low-level input voltage v ilc v ss C 0.3 v dd v*3 v dd = 2.7 v v ss C 0.2 v dd *3 high-level output voltage v ohc i oh = C1 ma 0.8 v dd Cv dd v*5 v dd = 2.7 v, i oh = C0.5 ma 0.8 v dd Cv dd *5 low-level output voltage v olc i ol = 1 ma v ss C 0.2 v dd v*5 v dd = 2.7 v, i ol = 0.5 ma v ss C 0.2 v dd *5 high-level input voltage v ihs 0.85 v dd C v dd *4 v dd = 2.7 v 0.8 v dd C v dd *4 low-level input voltage v ils v ss C 0.15 v dd *4 v dd = 2.7 v v ss C 0.2 v dd *4 input leakage current i li v in = v dd or v ss C1.0 C 1.0 m a*6 output leakage current i lo C3.0 C 3.0 m a*7 lcd driver on resistance r on ta = 25 cv 5 = C14.0 v C 2.0 3.0 k w v dd level v 5 = C8.0 v C 3.0 4.5 static current consumption i ssq v in = v dd or v ss C 0.01 5.0 m av ss i 5q v 5 = C18.0 v (v dd level) C 0.01 15.0 m av 5 input pin capacity c in ta = 25 c, f = 1 mhz C 5.0 8.0 pf *3 *4 oscillation frequency f osc ta = 25 cv dd = 5 v 18 22 26 khz *9 v dd = 2.7 v 18 22 26 recommended operation cmos schmitt seg n com n *8 item symbol condition min. typ. max. unit pin used input voltage v dd triple boosting 2.4 C 6.0 v *10 quadruple boosting 2.4 C 4.5 booster output voltage v out triple voltage conversion (v dd level) C18.0 C C v v out voltage regulator operation v out (v dd level) C18.0 C C6.0 v v out voltage voltage follower operation v5 (v dd level) C18.0 C C6.0 v *11 voltage C16.0 C C4.5 v reference voltage v reg ta = 25 c (v dd level) C2.75 C2.55 C2.35 v built-in power circuit for the mark *, refer to p. 1C25
s1d15300 series rev.1.4 epson 5C29 ta = 25 c item symbol condition min. typ. max. unit note s1d15300/ v dd = 5.0v, v 5 C v dd = C8.0 v, dual boosting 4170 s1d15305 v dd = 3.0v, v 5 C v dd = C8.0 v, triple boosting 4880 s1d15301 v dd = 5.0v, v 5 C v dd = C11.0 v, triple boosting 96 160 i dd v dd = 3.0v, v 5 C v dd = C11.0 v, quadruple boosting 118 190 m a *13 s1d15302 (1) v dd = 5.0v, v 5 C v dd = C11.0 v, triple boosting 95 160 v dd = 3.0v, v 5 C v dd = C11.0 v, quadruple boosting 114 190 s1d15303 v dd = 3.0v, v 5 C v dd = C5.0 v, dual boosting 3050 s1d15304 v dd = 3.0v, v 5 C v dd = C5.0 v, dual boosting 3255 ta = 25 c item symbol condition min. typ. max. unit note s1d15300/ v dd = 5.0v, v 5 C v dd = C8.0 v 24 40 s1d15305 v dd = 3.0v, v 5 C v dd = C8.0 v 22 35 s1d15301 v dd = 5.0v, v 5 C v dd = C11.0 v 40 65 i dd v dd = 3.0v, v 5 C v dd = C11.0 v 36 60 m a *12 s1d15302 (1) v dd = 5.0v, v 5 C v dd = C11.0 v 39 65 v dd = 3.0v, v 5 C v dd = C11.0 v 32 55 s1d15303 v dd = 3.0v, v 5 C v dd = C5.0 v 20 35 s1d15304 v dd = 3.0v, v 5 C v dd = C5.0 v 20 35 dynamic current consumption (2) when the built-in power supply is on dynamic current consumption (1) when the built-in power supply is off current consumption during power save mode v ss = 0 v, v dd = 2.7 to 5.5 v ta=25 c item symbol condition min. typ. max. unit note during sleep i dds1 s1d15300, s1d15301, s1d15302 0.01 1 m a during standby i dds2 s1d15300, s1d15301, s1d15302 10 20 typical current consumption characteristics (reference data) ? dynamic current consumption (1) when lcd external power mode lamp is on condition: remarks: ] 12 80 60 40 20 0 1234567 (ua) i dd (1) (i ss +15) v dd (v) the built-in power supply is off and an external power supply is used. s1d15300/s1d15305 v 5 -v dd =e8.0v s1d15301 v 5 -v dd =e11.0v s1d15302 v 5 -v dd =e11.0v s1d15303 v 5 -v dd =e6.0v s1d15304 v 5 -v dd =e6.0v ta=25 c s1d15300/s1d15305 s1d15303, s1d15304 s1d15301, s1d15302
s1d15300 series 5C30 epson rev.1.4 ? dynamic current consumption (2) when the lcd built-in power circuit lamp is on condition: remarks: ] 13 200 150 100 50 0 1234567 (ua) i dd (1) v dd (v) the built-in power circuit is on. s1d15300/s1d15305: v 5 -v dd =e8.0 v, triple boosting s1d15301: v 5 -v dd =e11.0 v, quadruple boosting s1d15302: v 5 -v dd =e11.0 v, quadruple boosting s1d15303: v 5 -v dd =e5.0 v, dual boosting s1d15304: v 5 -v dd =e5.0 v, dual boosting ta=25 c s1d15301, s1d15302 s1d15300/s1d15305 s1d15303, s1d15304 *1 though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during acc ess from the microprocessor. *2 v dd and v 5 operating voltage range. (refer to fig. 10.) the operating voltage range applies if an external power supply is used. *3 a0, d0 - d5, d6, d7 (si), rd (e), wr (r/w), cs1, cs2, fr, m/s, c86, p/s and dof pins *4 cl, scl (d6) and res pins *5 d0 - d5, d6, d7 (si), fr, frs, dyo, dof and cl pins *6 a0, rd (e), wr (r/w), cs1, cs2, m/s, res, c86 and p/s pins *7 applies when the d0 - d7, fr, cl, dyo and dof pins are in high impedance, *8 resistance value when 0.1 v is applied between the output pin segn or comn and each power supply pin (v1, v2, v3, v4). this is specified in the operating voltage (2) range. r on = 0.1 v/ d i ( d i: current flowing when 0.1 v is applied in the on status.) *9 for the relationship between oscillation frequency and frame frequency, refer to fig. 9. *10 for triple or quadruple boosting using the on-chip power useing the primary-side power supply v dd must be used within the input voltage range. *11 the voltage regulator adjusts v 5 within the voltage follower operating voltage range. *12, *13 current that each ic unit consumes. it does not include the current of the lcd panel capacity, wiring capacity, etc. this is current consumption under the conditions of display data = checker, display on, s1d15300 = 1/33 duty (1/6 bias), and s1 d15301 and s1d15302 = 1/65 duty. (1/8 bias) *12 applies to the case where the on-chip oscillator circuit is used and no access is made from the microprocessor. *13 applies to the case where the on-chip oscillator circuit and the on-chip power circuit are used and no access is made from t he microprocessor. the current flowing through voltage regulation resistors (r1, r2 and r3) is not included. the current consumption, when the on-chip voltage booster is used, is for the power supply v dd . ? relationship between oscillation frequency and frame frequency the relationship between oscillation frequency f osc and lcd frame frequency, f f can be obtained by the following expression. (f f does not indicate the fr signal cycle but the ac cycle.) fig. 9 relationship between clock (f cl ) and frame frequency f f duty f cl f f s1d15300 1/33 f osc /8 f osc /(8 * 33) s1d15301 1/65 f osc /4 f osc /(4 * 65) s1d15302 s1d15303 1/17 f osc /8 f osc /(8 * 17) s1d15304 1/9 f osc /8 f osc /(8 * 9) s1d15305 1/35 f osc /8 f osc /(8 * 35)
s1d15300 series rev.1.4 epson 5C31 fig 10 ? current consumption at access idd (2) - microprocessor access cycle fig. 11 -20 -15 -10 -5 0 2468 3.5 -16 -11 2.4 [v] v5-v dd v dd [v] operating range this indicates current consumption when data is always written on the checker pattern at fcyc. when no access is made, only idd (1) occurs. ?v ss and v 5 operating voltage range 0 0.01 0.1 1 10 10 1 0.1 0.01 [ma] i dd (2) fcyc [mhz] s1d15300, s1d15303, s1d15304, s1d15305 condition: s1d15300/s1d15305 v 5 -v dd =-8.0v, triple boosting s1d15301 v 5 -v dd =-11.0v, quadruple boosting s1d15302 v 5 -v dd =-11.0v, quadruple boosting s1d15303 v 5 -v dd =-6.0v, dual boosting s1d15304 v 5 -v dd =-6.0v, dual boosting ta = 25?c s1d15301, s1d15302
s1d15300 series 5C32 epson rev.1.4 ac characteristics (1) system buses read/write characteristics i (8080-series microprocessor) v dd = 5.0 v 10%, ta = C40 to +85 c d0~d7 (read) d0~d7 (write) wr,rd cs1 (cs2="1") a0 t aw8 t ah8 t cyc8 t cclw t cclr t ds8 t dh8 t acc8 t ch8 t cchw t cchr parameter signal symbol condition min. max. unit address hold time a0 t ah8 19 C ns address setup time t aw8 15 C ns system cycle time t cyc8 450 C ns control low pulse width (wr) wr t cclw 60 C ns control low pulse width (rd) rd t cclr 140 C ns control high pulse width (wr) wr t cchw 200 C ns control high pulse width (rd) rd t cchr 140 C ns data setup time t ds8 40 C ns data hold time t dh8 15 C ns rd access time d0 to d7 t acc8 cl=100pf C 140 ns output disable time t ch8 10 100 ns parameter signal symbol condition min. max. unit address hold time a0 t ahigh8 10 C ns address setup time t aw8 10 C ns system cycle time t cyc8 166 C ns control low pulse width(wr) wr t ccloww 30 C ns control low pulse width(rd) rd t cclowr 70 C ns control high pulse width (wr) wr t cchighw 100 C ns control high pulse width (rd) rd t cchighr 70 C ns data setup time t ds8 20 C ns data hold time t dhigh8 10 C ns rd access time d0 to d7 t acc8 cl=100pf C 70 ns output disable time t chigh8 10 50 ns v dd = 2.7 v to 4.5 v, ta = C40 to +85 c notes: 1. the input signal rise/fall time (t r , t f ) is specified at 15 ns or less. when system cycle time is used at a high speed, it is specified by t r + t f ( t cyc8 - t cclw ) or t r + t f ( t cyc8 - t cclr - t cchr ). 2. every timing is specified on the basis of 20% and 80% of v dd . 3. t ewhr and t ewhw are specified by the overlap period in which cs1 is 0 (cs2 = 1) and wr and rd are 0. 4. when it is expected that vss ranges from -2.4 v to -4.5 v during the operation, increase all the above specifications from -2 .7 v to -4.5 v by 30% before the operation.
s1d15300 series rev.1.4 epson 5C33 (2) system buses read/write characteristics ii (6800-series microprocessor) parameter signal symbol condition min. max. unit system cycle time t cyc6 166 C ns address setup time a0 t aw6 10 C ns address hold time w/r t ah6 10 C ns data setup time t ds6 20 C ns data hold time d0 to d7 t dh6 10 C ns output disable time t oh6 cl=100pf 10 50 ns access time t acc6 C70ns enable read e t ewhr 70 C ns low pulse width write t ewhw 30 C ns enable read e t ewlr 70 C ns high pulse width write t ewlw 100 C ns v dd = 5.0 v 10%, ta = C40 to +85 c v dd = 2.7 v to 4.5 v, ta = C40 to +85 c a0 cs1 (cs2="1") e d0~d7 (wr1te) d0~d7 (read) t aw6 t ah6 t ewhw t ewhr t cyc6 t acc6 t oh6 t ds6 t ewlw t ewlr t dh6 r/w notes: 1. the input rise/fall time (t r , t f ) is specified at 15 ns or less. when the system cycle time is used at a high speed, it is specified by t r + t f (t cyc6 - t ewlw - t ewhw ) or tr + tf (t cyc6 - t ewlr - t ewhr ). 2. every timing is specified on the basis of 20% and 80% of v dd . 3. t ewhr and t ewhw are specified by the overlap period in which cs1 is 0 (cs2 = 1) and e is 1. 4. when it is expected that vss ranges from -2.4 v to -4.5 v during the operation, increase all the above specifications from -2 .7 v to -4.5 v by 30% before the operation. parameter signal symbol condition min. max. unit system cycle time t cyc6 450 C ns address setup time a0 t aw6 15 C ns address hold time r/w t ah6 19 C ns data setup time t ds6 40 C ns data hold time d0 to d7 t dh6 15 C ns output disable time t oh6 cl=100pf 10 100 ns access time t acc6 C 140 ns enable read e t ewhr 140 C ns low pulse width write t ewhw 60 C ns enable read e t ewlr 140 C ns high pulse width write t ewlw 200 C ns
s1d15300 series 5C34 epson rev.1.4 (3) serial interface notes: 1. the input signal rise and fall times must be within 15 nanoseconds. 2. all signal timings are limited based on 20% and 80% of v dd voltage. 3. when it is expected that vss ranges from -2.4 v to -4.5 v during the operation, increase all the above specifications from -2 .7 v to -4.5 v by 30% before the operation. parameter signal symbol condition min. max. unit serial clock cycle scl t scyc 250 C ns serial clock high pulse width t shw 100 C ns serial clock low pulse width t slw 75 C ns address setup time a0 t sas 50 C ns address hold time t sah 200 C ns data setup time si t sds 50 C ns data hold time t sdh 50 C ns cs serial clock time cs t css 30 C ns t csh 100 C v dd = 5.0 v 10%, ta = C40 to +85 c v dd = 2.7 to 4.5v, ta = C40 to +85 c parameter signal symbol condition min. max. unit serial clock cycle scl t scyc 500 C ns serial clock high pulse width t shw 200 C ns serial clock low pulse width t slw 150 C ns address setup time a0 t sas 100 C ns address hold time t sah 400 C ns data setup time si t sds 100 C ns data hold time t sdh 100 C ns cs serial clock time cs t css 60 C ns t csh 200 C scl si a0 cs1 (cs2="1") t sds t shw t sdh t slw t scyc t sas t sah t css t csh tr tf
s1d15300 series rev.1.4 epson 5C35 (4) display control timing notes: 1. the otput timing is valid in master mode. 2. every timing is specified on the basis of 20% and 80% of v dd . (5) reset timing note: the reset timing is specified on the basis of 20% and 80% of v dd. output timing v dd = 5.0 v 10%, ta = C40 to +85 c output timing v ss = 0 v, v dd = 2.7 v to 4.5 v, ta = C40 to +85 c parameter signal symbol condition min. typ. max. unit fr delay time fr t dfr cl = 50 pf C 10 40 ns dyo high delay time dyo t doh C 40 100 ns dyo low delay time t dol C 40 100 ns parameter signal symbol condition min. typ. max. unit fr delay time fr t dfr cl = 50 pf C 15 80 ns dyo high delay time dyo t doh C 70 200 ns dyo low delay time t dol C 70 200 ns parameter signal symbol condition min. typ. max. unit reset time t r 0.5 C C m s reset low pulse width res t rw 0.5 C C m s v dd = 5.0 v 10%, ta = C40 to +85 c v dd = 2.7 v to 4.5 v, ta = C40 to +85 c parameter signal symbol condition min. typ. max. unit reset time t r 1.0 C C m s reset low pulse width res t rw 1.0 C C m s cl (out) fr t dfr t doh t dol dyo t rw t r end of reset during reset res internal circuit status
s1d15300 series 5C36 epson rev.1.4 v cc gnd mpu port 1 port 2 res v dd v ss c86 s1d15300 p/s si scl a0 a1 to a7 decoder a0 cs1 cs2 res reset v dd or gnd v ss v dd 11. mpu interface (for reference) the s1d15300 series chips can directly connect to 8080 and 6800-series microprocessors. also, serial interfacing requires less signal lines between them. when multiple chips are used in the s1d15300 series they can be connected to the microprocessor and one of them can be selected by chip select. 8080-series microprocessors 6800-series microprocessors serial interface v cc gnd a0 a1 to a7 iorq d0 to d7 rd wr res mpu decoder reset v dd a0 s1d15300 v ss cs1 cs2 c86 p/s v ss v dd v ss v dd d0 to d7 rd wr res v cc gnd a0 a1 to a15 vma d0 to d7 e r/w res mpu decoder v dd a0 d0 to d7 e r/w res s1d15300 v ss cs1 cs2 c86 p/s reset v dd v dd v ss v dd
s1d15300 series rev.1.4 epson 5C37 12. connection between lcd drivers the lcd panel display area can easily be expanded by use of multiple s1d15300 series chips. the s1d15300 series can also be co nnected to the common driver (s1d16305). s1d15300 to s1d15301 s1d15302 to s1d15302 dof cl dyo s1d15301 (master) s11d16305 fr fr doff dio yscl m/s v dd dof cl dyo s1d15300 (slave) s1d15300 (master) fr fr cl dyo dof m/s v dd m/s v ss dof cl dyo s1d15302 (slave) s1d15302 (master) fr fr cl dyo dof m/s v dd m/s v ss s1d15301 to s1d16305 (s1d16305)
s1d15300 series 5C38 epson rev.1.4 s1d15300d00a * seg (100) seg (100) com (33) com (17) com (16) s1d15300d10a * s1d15300 : 100 33dot 132 65 dot s1d16700 s1d15301 seg(132) vdd fr cl dyo dof m/s com(65) doff dio yscl fr s1d15302 : 200 65 dot s1d15302 seg(100) vdd m/s fr dof cl s1d15302 seg(100) m/s fr dof cl com(33) com(32)
s1d15300 series rev.1.4 epson 5C39 dimensional outline drawing of the flexible substrate (an example) the dimensions are subject to change without prior notice. note 1) regist position tolerance = 0.3 note 2) product pitch: 9ip (42.75mm) note 3) lot no. is to be indicated in columns in the product. specifications ?base: u-rexs, 75 m ?copper foil: electrolytic copper foil, 35 m ?sn plating ?product pitch: 91p (42.75mm) ?solder resist positional tolerance: 0.3 (mold, marking area) (mold, marking area) output terminal pattern shape (mold, marking area) (mold, marking area) ic center
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in pursuit of ?aving?technology , epson electronic devices. our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers?dreams. epson is energy savings. 4.5mm notice no parts of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export licence from teh ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2001, all rights reserved. i8088 and i8086 are registered trademarks of intel corporation. z80 is registered trademark of zilog corporation. v20 and v30 are registered trademarks of nippon electric corporation.
mf424 - 21 technical manual s1d15000 series technical manual ieee1394 controller s1r75801f00a technical manual s1d15000 series epson electronic devices website electronic devices marketing division first issue december,1992 u printed may,2001 in japan h b 4.5mm this manual was made with recycle paper, and printed using soy-based inks. technical manual lcd driver with ram s1d15000 series http://www.epson.co.jp/device/

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